Gain control for wireless receiver

ABSTRACT

Various embodiments are disclosed relating to a gain control for a wireless receiver. In an example embodiment, a wireless receiver is provided that may include an analog gain circuit adapted to provide a variable analog gain on a received input signal, an analog to digital converter (ADC) having an input coupled to an output of the analog gain circuit, and a digital gain circuit having an input coupled to an output of the ADC and adapted to provide a variable digital gain on a received digital signal from the ADC. According to an example embodiment, the wireless transceiver may decrease a gain of the analog gain circuit while maintaining a gain of the digital gain circuit substantially constant for a receiver input signal level that increases from a first input signal level up to at least a first test signal level. In addition, in an example embodiment, the wireless receiver may also decrease a gain of the analog gain circuit while maintaining a gain of the digital gain circuit substantially constant for a signal level of the input signal that increases from a first input signal level up to at least a blocker test signal level.

BACKGROUND

Wireless transceivers are used in a wide variety of wireless systems. Awireless transceiver may typically include a wireless receiver forreceiving and demodulating signals, and a transmitter for modulatingsignals for transmission. Wireless transceivers may be capable oftransmitting on different frequencies or bands. It may be a challenge insome cases for receivers to sufficiently reject an image or blockersignal while making use of a dynamic range of the receiver components.

SUMMARY

Various embodiments are disclosed relating to wireless systems, and alsorelating to a gain control for a wireless receiver.

According to an example embodiment, a wireless receiver is provided thatmay include an analog gain circuit adapted to provide a variable analoggain on a received input signal, an analog to digital converter (ADC)having an input coupled to an output of the analog gain circuit, and adigital gain circuit having an input coupled to an output of the ADC andadapted to provide a variable digital gain on a received digital signalfrom the ADC. According to an example embodiment, the wirelesstransceiver may decrease a gain of the analog gain circuit whilemaintaining a gain of the digital gain circuit substantially constantfor a signal level of the input signal that increases from a first inputsignal level up to at least a first test signal level (e.g., blockertest signal level or image test signal level). In addition, in anexample embodiment, the wireless receiver may also decrease a gain ofthe analog gain circuit while maintaining a gain of the digital gaincircuit substantially constant for a signal level of the input signalthat increases from a first input signal level up to at least a blockertest signal level.

For example, by decreasing the analog gain while holding the digitalgain constant up to a blocker test and/or image test, this may allow thereceiver to better accommodate large blocker and/or image signals andpass the blocker and/or image tests. Also, by thereafter holding theanalog gain constant and decreasing the digital gain as the receiverinput signal level increases, this may allow an input signal level tothe ADC to increase, which may a better use of the full dynamic range ofthe ADC.

According to another example embodiment, a method of varying gain in awireless receiver is provided. The wireless receiver may include ananalog-to-digital converter (ADC), an analog gain circuit coupled to aninput of the ADC, and a digital gain circuit coupled to an output of theADC. The method may include varying a gain of the analog gain circuit tomaintain a substantially constant signal level at an input to the ADCwhile maintaining the gain of the digital gain circuit at asubstantially constant level as the input signal to the receiver variesbetween a first input signal level up to a first test signal level. Themethod may also include maintaining the gain of the analog gain circuitsubstantially constant while decreasing the gain of the digital gaincircuit for a receiver input signal level that increases from the firsttest signal level up to at least a second input signal level.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a wireless system according to an exampleembodiment.

FIG. 2 is a block diagram of a wireless transceiver according to anexample embodiment.

FIG. 3 is a block diagram illustrating a local oscillator (LO) frequencysynthesizer of FIG. 2 according to an example embodiment.

FIG. 4 is a block diagram of a receiver according to an exampleembodiment.

FIG. 5 is a chart illustrating an example gain control for the receiverof FIG. 4 according to an example embodiment.

FIG. 6 is a flow chart illustrating operation of a wireless receiveraccording to an example embodiment.

FIG. 7 is a flow chart illustrating operation of a wireless receiveraccording to another example embodiment.

DETAILED DESCRIPTION

FIG. 1 is a block diagram of a wireless system according to an exampleembodiment. Wireless system 100 may include a wireless transceiver(transmitter/receiver) 102 for transmitting and receiving radio orwireless signals. A baseband processor 112 is coupled to wirelesstransceiver 110 to perform various types of processing and overallcontrol of system 100, and may perform other tasks. Baseband processor112 may include a controller, and may include for example, an audiocodec to process audio signals, a video or image processing codec (e.g.,an MPEG4 compression and/or decompression module), and other componentsor blocks, not shown.

An antenna 110 may be provided to receive and transmit radio signals orelectromagnetic signals. A transmitter/receiver (TR) switch 108 mayselect either the transmit or receive mode for the antenna 110. Signalsoutput by wireless transceiver 102 to be transmitted may be amplified byamplifier 104 and then transmitted via antenna 110. Signals received viaantenna 110 may be filtered by a SAW (surface acoustic wave) filter 106(or other filter) and then input to transceiver 102. At transceiver 102,the received signals may be processed or demodulated, which may includedown-converting the signals to an intermediate frequency (IF) and thendown-converting to baseband or other frequency, digital detection ofdata and other signal processing. Likewise, digital data to betransmitted may be received by transceiver 102 from baseband processor112. Wireless transceiver 110 may modulate the digital data frombaseband processor 112 onto a selected channel or frequency (or range orspectrum of frequencies) for transmission over antenna 110.

A variety of blocks or peripherals may be coupled to baseband processor112. For example, a memory 114, such as a Flash memory or Random AccessMemory (RAM), may store information. A microphone 118 and speaker 116may allow audio signals to be input to and output by wireless system100, such as for a cell phone or other communications device. A keypad120 may allow a user to input characters or other information to beprocessed by wireless system 100. A camera 122 or other optical devicemay be provided to allow users to capture photos or images that may beprocessed and/or stored by system 100 in memory or other storagelocation. Wireless system 100 may also include a display 124, such as aliquid crystal display for example, to display information (text,images, etc.). A variety of other peripherals 126 may be coupled tobaseband processor 112, such as a memory stick, an audio player, aBluetooth wireless transceiver, a USB (Universal Serial Bus) port, orother peripheral. These are merely a few examples of the types ofdevices or peripherals that may be provided as part of wireless system100 or coupled to baseband processor 112, and the disclosure is notlimited thereto.

Wireless system 100 may be used in a variety of systems or applications,such as a mobile or cellular phone, a wireless local area network (WLAN)phone, a wireless personal digital assistant (PDA), a mobilecommunications device, or other wireless device. In an exampleembodiment, wireless system 100 may be capable of operating in a varietyof transmit/receive frequencies or frequency bands and for a variety ofdifferent standards or communications protocols. Although not required,wireless system 100 may be a multi-band wireless system capable oftransmitting or receiving signals on one of a plurality of frequenciesor bands. For example, wireless system 100 may operate at or around 1900MHz for WCDMA (Wide-Band Code Division Multiple Access) or PCS (PersonalCommunications Services), at or around 1800 MHz for DCS (DistributedCommunication Services) (these frequencies may be considered an upperband of frequencies), at 850 MHz for GSM (Global System for Mobilecommunication), at or around 900 MHz for EGSM (Extended GSM) (thesefrequencies may be considered a lower band of frequencies). These aremerely some example frequencies, and the system 100 may operate at manyother frequencies and standards.

FIG. 2 is a block diagram of a wireless transceiver according to anexample embodiment. Wireless transceiver 102 may include a transmitter202 to modulate and transmit data, and a receiver 204 to receive anddemodulate data. A crystal oscillator 210 may generate a signal at aconstant frequency, such as 26 MHz or other frequency (26 MHz is merelyan example and other frequencies may be used). A local oscillator (LO)frequency synthesizer 212 may generate a synthesized frequency signal(f_(synth)) at a selected one of a plurality of frequencies, e.g., basedon a selected channel. The synthesized frequency signal (f_(synth)) maybe used by both the transmitter 202 and receiver 204 as a referencesignal.

A digital modulator 214 may receive digital data and output data ontoone or more paths. According to an example embodiment, transmitter 102may modulate received data using a variety of Phase Shift Keying (PSK),such as 8PSK, Quadrature Amplitude Modulation (QAM), etc., in which datamay be modulated using both phase modulation and amplitude modulation.Digital modulator 214 may alternatively modulate received data usingphase modulation or frequency modulation, or variations thereof, such asGaussian-Filtered Minimum Shift Keying (GMSK), and the like. Accordingto an example embodiment, for such a phase modulation or frequencymodulation or GMSK modulation, or the like, the amplitude of the signaloutput by transmitter 202 may be, for example, set to a constantamplitude or level.

To be able to accommodate different frequencies and different channels,fynth may be a variable frequency between, for example, 1.752 GHz and2.0 GHz. This is merely an example frequency range, and otherfrequencies or frequency ranges may be used. f_(synth) may be frequencydivided by frequency divider 218 to generate a transmit referencefrequency (f_(TXREF)). In an example embodiment, frequency divider 218may be a divide by 8. Therefore, f_(TXREF) may be generated asf_(synth)/8 and in such case, f_(TXREF) may vary between 219 MHz and 250MHz, for example.

Digital modulator 214 may receive digital data and output signals onboth lines 217 and 219 to a variable rate adapter 216. In an exampleembodiment, digital modulator 214 may use f_(TXREF) as a clock. Asnoted, f_(TXREF) may be a variable frequency. Variable rate adapter 216may compensate for the variable rate clock (f_(TXREF)) that may be usedby digital modulator 214, e.g., such that signals output by variablerate adapter 216 may be output at a constant frequency even though clockfor digital modulator 214 may vary.

In order to perform both phase modulation (PM) (or a variation thereof)and amplitude modulation (AM) on the received digital data, such as for8PSK or QAM or the like, variable rate adapter 216 may output signalsonto two paths including: 1) a PM path 231 to perform phase modulationbased on received data; and 2) an AM path 233 to perform amplitudemodulation based on the received data.

The PM path will now be discussed. In the PM path 231, a transmitfrequency synthesizer 201 may include a phase-locked loop (PLL) and adelta-sigma modulator 238. Within the transmit frequency synthesizer201, a voltage controlled oscillator (VCO) 220 may output a signal at anoperating frequency for a selected channel for a selected band of aservice (e.g., channel number 2 at a center frequency of 1710.2 MHz forDCS). For example, a base station or Access Point (AP) may assign thewireless system 100 a channel to use for data transmission. As describedin more detail below, VCO 220 may output a range of frequencies or amodulated frequency spectrum for the selected channel, with the databeing modulated onto the frequency spectrum. VCO 220 may also include again, or an amount which the output spectrum from VCO 220 is amplified.This gain (K) of VCO 220 may be referred to as K_(VCO). In an exampleembodiment, the gain of VCO 220 (K_(VCO)) may be calibrated.

The frequency spectrum output by VCO 220 may then be amplified by upperband amplifier 222 for transmission via antenna 110. The frequencyspectrum output by VCO 220 may also be divided by two by frequencydivider 224 and then amplified by lower band amplifier 226 for datatransmission over antenna 110. Thus, according to an example embodiment,a frequency spectrum for a selected channel in the upper band offrequencies may be amplified and output by amplifier 222, while afrequency spectrum for a selected channel in the lower band offrequencies may be amplified and output by amplifier 226.

As noted above, transmit frequency synthesizer 201 may include a PLL.According to an example embodiment, the phase-locked loop (PLL) withintransmit frequency synthesizer 201 may control or lock the VCO 220 to adesired or selected operating frequency (channel). The PLL withintransmit frequency synthesizer 201 may include, for example, aphase-frequency detector (PFD) 230, a charge pump 232 and a programmablelow pass filter (LPF) 234 (also referred to as a loop filter), and mayinclude other or different components, since this is merely an examplePLL. The output (f_(VCO1)) of VCO 220 may include an operating frequencyof a selected channel (e.g., center frequency). An integer-N (frequency)divider 236 is coupled to the feedback loop of the PLL, and may divide areceived frequency by a selected divider number (e.g., an integer,either 7 or 8). The output frequency of VCO 220 (f_(VCO1)) is divided bya divider number (N2) of integer-N divider 236 that is selected by a1-bit delta-sigma (ΔΣ) modulator 238 via line 241. Integer-N divider 236may be considered to be a multi-modulus divider (MMD) since the dividernumber (N2) used by integer-N divider 236 may be one of multipledifferent numbers (integers). The transmit frequency synthesizer 201 mayprovide a selected fractional-N divide ratio (average N2) by dynamicallyswitching the divider number (N2) of integer-N divider 236 between twoor more integer numbers. Thus, transmit frequency synthesizer 201 may beconsidered to be a fractional-N frequency synthesizer.

In an example embodiment, the divider number used by integer-N divider236 may be either 7 or 8, based on the signal (bit) received fromdelta-sigma modulator 238 via line 241 (e.g., a 0 output on line 241 bymodulator 238 to indicate a 7 for the divider number N2, while a 1indicating an 8 for divider number N2). Therefore, according to anexample embodiment, the operating frequency output by VCO 220 may bef_(VCO1)=N2*f_(TXREF). The integer divider numbers of 7 or 8 may allowonly two operating frequencies to be output by VCO 220 for a particularf_(TXREF) (transmitter reference frequency). However, by varying theselected integer divider number used by integer-N divider 236, almostany (average) fractional-N divide ratio (average N2) between 7 and 8 maybe obtained, which may allow VCO 220 to output a range of frequencies.

In order to lock or control the VCO 220 to a desired to selected outputfrequency (for the selected channel), a f_(synth) (and thus f_(TXREF))is selected, and an average fractional-N divide ratio (average N2) isselected between 7 and 8 (in this example embodiment, although anynumbers may be used) that will provide the selected operating frequencyoutput by VCO 220. For example, if a transmit operating frequency isassigned or selected of 1.661 GHz, then a transmit reference frequency(f_(TXREF)) may be selected of 220 MHz, and a (average) fractional-Ndivide ratio of 7.55 may be used. Thus, in this example, a VCO output(operating frequency for the channel) is thus obtained as:f_(VCO1)=N2(average)*f_(TXREF), which in this case may be calculated as:f_(VCO1)=7.55*220 MHz=1.661 GHz, which is the desired operatingfrequency (e.g., center frequency for the assigned transmissionchannel).

The fractional-N divide ratio (7.55 in this example) between 7 and 8 maybe obtained by using delta sigma modulator 238 to vary the dividernumber (N2) of integer-N divider 236 to divide by 7 and divide by 8 anappropriate amount or percentage to obtain the selected (average)fractional-N divide ratio (average N2). For example, to obtain afractional-N divide ratio of 7.5, then the integer-N divider 236 woulddivide by 7 half of the time, and divide by 8 the other half of the time(50% duty cycle, half zeroes, half ones). By changing the duty cycle orpercentage of zeros and ones output by delta sigma modulator 238 vialine 241, the frequency (f_(VCO1)) received via line 243 may be dividedby a selected fractional-N divide ratio (e.g., 7.55).

The fractional portion (0.55 in this example) of the selected fractionaldivider number (7.55 in this example) may be input to combiner 240.Combiner 240 may add or combine the fraction 244 (0.55 in this example)with a data signal (to provide phase modulation) output by variable rateadapter 216. The output of combiner 240 may control delta-sigmamodulator 238 to obtain the (average) selected fractional-N divide ratiofor transmit frequency synthesizer 201.

In an example embodiment, VCO 220 may not necessarily output a singletone or frequency, but rather, may output a modulated frequencyspectrum, such as a phase modulated spectrum. In an example embodiment,the delta sigma modulator 238 may control the integer-N divider 236 tovary the divider number (N2) around the selected fractional divide ratioso as to cause VCO 220 to generate a phase modulated frequency spectrum.In part, the delta sigma modulator 238 may be controlled based onsignals output via line 217 from digital modulator 214 (e.g., to allowphase modulation of the output signal output from VCO 220), and passedthrough (e.g., after compensation) by variable rate adapter 216. Thismay allow the output from VCO 220 (f_(VCO1)) to be a phase modulatedfrequency spectrum around a center frequency for the selected channel(the operating frequency selected by the fractional-N divide ratio, suchas 7.55, for example).

An operation of the example PLL of transmit frequency synthesizer 201 oftransmitter 202 will be briefly described. The transmitter referencefrequency (f_(TXREF)) is input as a reference signal to PFD 230. Thedivided frequency signal output on line 245 from divider 236 is a secondinput to PFD 230. PFD 230 may generate an output signal(s) based on thephase difference between its two input signals. For example, an upsignal or a down signal may be output by PFD 230 based on whether thedivided frequency signal on line 245 leads or lags the referencefrequency signal (f_(TXREF)), respectively. Charge pump 232 may generatepositive or negative charge pulses based on whether the dividedfrequency signal on line 245 leads or lags the reference signal(f_(TXREF)), respectively. Programmable low pass filter (LPF) 234 mayintegrate or accumulate the charge pulses to generate a voltage, which,for example, may indicate the amount that the divided frequency signalon line 245 leads or lags the reference signal (f_(TXREF)). The voltageoutput by LPF 234 may control or adjust the frequency (f_(VCO1)) outputby VCO 220.

Thus, via the PM path 231, VCO 220 may output a phase modulatedfrequency spectrum, which is then amplified and output by upper bandamplifier 222. Similarly, the output from VCO 220 is divided by two bydivider 224, and is then amplified and output by lower band amplifier226.

In an example embodiment, LPF 234 (of the PLL) may set the loopbandwidth of the PLL. If the bandwidth of the LPF is too narrow, part ofthe output spectrum from VCO 220 may be clipped or distorted. Likewise,if the bandwidth of LPF 234 is too wide, this may introduce anunacceptable amount of noise into the system. Therefore, according to anexample embodiment, a relatively narrow bandwidth may be used for LPF234, such as 200 KHz (this is merely an example, and other bandwidthsmay be used). Also, in an example embodiment, digital modulator 214 mayinclude an equalizer to account for some clipping or signal distortionthat may occur due to the 200 KHz bandwidth of low pass filter (LPF)234. In an example embodiment, LPF 234 may be an R-C(resistor-capacitor) filter, which may be calibrated.

In cases in which the transmitted signal may be both phase modulated andamplitude modulated, such as for 8PSK, QAM or the like, the AM path 231may perform amplitude modulation on the phase modulated spectrum basedon the received digital signals. As noted, the digital data is receivedby digital modulator 214. The digital modulator 214 may output data viatwo paths, to provide both phase modulation (via PM path 231) andamplitude modulation (via AM path 233).

The AM path 233 will now be briefly described. Digital modulator 214outputs signals (e.g., via variable rate adapter 216) todigital-to-analog converter (DAC) 250. DAC 250 converts received digitalsignals to analog signals. The analog signals, which may represent orindicate an amplitude, are input to amplifiers 226 and 222. Amplifiers226 and 222 may amplitude modulate (or vary the amplitude) of the phasemodulated spectrum provided from the VCO 220 based upon the signalsreceived from DAC 250 via AM path 233. Thus, signals received via the AMpath 233 may control the amplitude or gain of the phase modulatedsignals (spectrum) output by transmitter 202. Therefore, amplifiers 222and 226 may output an amplitude and phase modulated signal (e.g.,frequency spectrum), according to an example embodiment.

In cases where only phase or frequency modulation is performed (such as,for example, GMSK for GSM and EGSM), then the amplitude value output bydigital modulator 214 to DAC 250 may be set to a constant level, toprovide a constant amplitude for the phase modulated spectrum output byamplifiers 222 and 226. In an embodiment, the constant amplitude used byDAC 250 for such modulations may be typically set to a maximum toprovide a high saturated output power.

Receiver 204 of wireless transceiver 102 (FIG. 2) will now be brieflydescribed. Wireless signals may be input to receiver 204, includingupper (or high) band signals received via line 257, and lower bandsignals received via line 259. These received signals may be amplifiedby low noise amplifier (LNA) 260. During normal operation, the receivedwireless signal may be down converted by mixer 262, based on thesynthesizer frequency (f_(synth)) output by LO frequency synthesizer 212(e.g., the received signal may be mixed with f_(synth) by mixer 262 togenerate an IF signal). In an embodiment, the received signal may thenbe down converted to an intermediate frequency (IF) of 200 KHz, forexample (although any frequency may be used for IF). The IF signal maybe input to receiver IF block 265 (which may include, for example,filters, gain control and other circuits) where IF processing isperformed. The signals output by receiver IF block 265 are input to areceiver DSP 266, which may include, for example, gain control anddigital signal processor to down convert the IF signal to baseband.Receiver DSP 266 may output in-phase and quadrature-phase receivesignals (RX_I, RX_Q, respectively). The receive signals (RX_I and RX_Q)may also be output to digital modulator 214 (connection not shown), andalso to an AM path delay adjustment circuit 268.

Wireless systems, at least in some cases, may be required to meet one ormore signal requirements. For example, some wireless technologies mayrequire wireless transmissions meet (or fall within) a spectral mask.

One issue that may arise for wireless systems that employ two types ofmodulation, such as both amplitude and phase or frequency modulation(e.g., such as 8PSK, QAM, etc.) is that there may be a mismatch in thetiming or delay for the phase modulation and amplitude modulation (ormore generally, a mismatch in the delay of a first modulation path and asecond modulation path). In some cases, if the mismatch in delay ortiming through the AM path and PM path of the transceiver issignificant, it may distort the output or transmitted signal such thatthe output signal does not meet one or more signal requirements (such asa spectral mask). Therefore, for example, to avoid violating a spectralmask or other signal requirements, it may be desirable for the delay (ortiming) through the AM path 231 and PM path 233 to be well matched.

According to an example embodiment, the receiver 204 of transceiver 102may be used to calibrate the delay or timing for the AM path 231 and PMpath 233 of transmitter 202. The transmitter reference frequencyf_(TXREF) may be divided by four by frequency divider 254. This dividedsignal (f_(TXREF)/4) may be input to mixer 256. Mixer 256 may up-convertthe frequency of the modulated transmit frequency spectrum (amplitudeand phase modulated output spectrum from amplifiers 222 and 226) toreceive frequencies (e.g., upper and/or lower band receive frequenciesthat can be processed by receiver 204). During delay path calibrationmode, the up-converted modulated transmit frequency spectrum is then fedor input to receiver 204 for processing. The transmit frequency spectrummay be down converted by mixer 262 to IF (e.g., 200 KHz), and processedby receiver IF block 265 and receiver DSP 266. The processed (ordemodulated) transmit spectrum may then be output via receive signals(RX_I and RX_Q). This processing of the signals at receiver 204 may beconsidered to be a form of demodulation, in an example embodiment.

The processed or demodulated transmit spectrum may then be analyzed byAM path delay adjustment circuit 268, e.g., to determine if thedemodulated transmit spectrum meets one or more signal requirements,such as determining if the demodulated transmit spectrum meets or fallswithin a required spectral mask. Alternatively, path delay adjustmentcircuit 268 may determine if there is a significant mismatch between thetiming or delay of the AM path 233 and PM path 231, for example. Pathdelay adjustment circuit 268 may then adjust the delay or timing of oneor both of the AM path 233 and PM path 231, e.g., if the demodulated (orprocessed) transmit spectrum does not meet the one or more signalrequirements or mask, or if there is a significant mismatch in thetiming or delay between the AM path 233 and PM path 231, for example.Path delay adjustment circuit 268 may adjust the delay or timing of theAM path 233 or the PM path 231, or both.

In another example embodiment, the gain of VCO 220 may be calibrated. Insuch case, in an example embodiment, the loop bandwidth of the PLL andLPF 234 may be well defined, and the delay through the PLL (PM path) andthe AM path may also be stable and well defined. As a result, this isone example where it may not be necessary to calibrate the modulationdelay paths (AM and PM paths). Thus, in an example embodiment, themodulation path delay calibration may be optional, and may be disabledor turned of in some cases.

In an example embodiment, path delay adjustment circuit 268 may be an AMpath delay adjustment circuit that may adjust the delay of the AM path233, based on the analysis or evaluation of the demodulated transmitspectrum (e.g., if the demodulated spectrum does not meet the signalrequirement or mask). For example, path delay adjustment circuit 268 mayadjust the delay provided by DAC 250 in AM path 233. This process may berepeated and re-calibrated, e.g., another modulated transmit frequencyspectrum signal may be up-converted by mixer 256 to the receivefrequency, and input to the receiver 204, where the spectrum may be downconverted to IF, down converted to baseband and processed (e.g.,demodulated). The demodulated or receive-processed transmit spectrum mayagain be evaluated or analyzed, and then a delay or timing may beadjusted in one or both AM path 233 and PM path 231, if necessary, toimprove the match in path delay or improve the quality of the outputsignal. In this manner, the AM path delay and PM path delay oftransmitter 202 may be calibrated (e.g., measured and adjusted) byfeeding the modulated transmit spectrum into the receiver 204 forprocessing.

FIG. 3 is a block diagram illustrating a local oscillator (LO) frequencysynthesizer of FIG. 2 according to an example embodiment. LO frequencysynthesizer 212 may be very similar to the transmit frequencysynthesizer 201 in FIG. 2. LO frequency synthesizer 212 may include aphase-locked loop (PLL) and a delta-sigma modulator 338. According to anexample embodiment, the phase-locked loop (PLL) within transmitfrequency synthesizer 201 may control or lock the VCO 320 to output adesired or selected synthesized frequency (f_(synth)), e.g., based on aselected channel. The synthesized frequency (f_(synth)) output by LOfrequency synthesizer 212 may be used as a reference frequency by thetransmitter 202 and receiver 204.

The PLL within LO frequency synthesizer 212 may include, for example, aphase-frequency detector (PFD) 330, a charge pump 332 and a programmablelow pass filter (LPF) 334 (also referred to as a loop filter), and mayinclude other or different components, since this is merely an examplePLL. The output (f_(VCO2)) of VCO 320 may include a tone or frequencythat is divided by 2 by frequency divider 335, to generate thesynthesized frequency (f_(synth)). An integer-N (frequency) divider 336is coupled to the feedback loop of the PLL, and may divide a receivedfrequency by a selected divider number (e.g., an integer, between 64 and79). The synthesized frequency (f_(synth)) on line 350 is then dividedby a divider number (N1) of integer-N divider 236 that is selected by adelta-sigma (ΔΣ) modulator 338 via line 357. Integer-N divider 336 maybe considered to be a multi-modulus divider (MMD) since the dividernumber (N1) used by integer-N divider 336 may be one of multipledifferent numbers (integers), e.g., between 64 and 79. The LO frequencysynthesizer 212 may provide a selected fractional-N divide ratio(average N1) by dynamically switching the divider number (N1) ofinteger-N divider 336 between two or more integer numbers. Thus, LOfrequency synthesizer 212 may be considered to be a fractional-Nfrequency synthesizer.

In an example embodiment, the divider number used by integer-N divider236 may be any number between 64 and 79, based on the signal receivedfrom delta-sigma modulator 338 via combiner 340. Combiner 340 maycombine the output from modulator 338 with an integer 304. A fraction302 may also be input to modulator 302. A 26 MHz reference input is usedas one input to PFD 330. The other input to PFD 330 is the output frominteger-N divider 336, via line 345. The PLL of LO frequency synthesizer212 operates similarly to the PLL of transmit frequency synthesizer 201,described above. In general, by varying the selected integer dividernumber used by integer-N divider 336, almost any (average) fractional-Ndivide ratio (average N1) between 64 and 79 may be obtained, which mayallow VCO 320 to output a range of frequencies. The PLL of LO frequencysynthesizer 212 may operate to control or lock the output frequency(f_(VCO2))=26 MHz*2*N1. Thus, the frequency output from VCO 320 (andthus the frequency of f_(synth)) may be generated based on a selectedaverage fractional-N divide ratio (average N1) for divider 336.

The frequency synthesizer signal (f_(synth)) may be input to mixer 262(FIG. 2) and to mixer 462 (FIG. 4) via line 350, and may be used as amixing signal to down convert upper band signals (e.g., PCS1900 andDCS1800 signals) to IF (e.g., 200 KHz), for example. In addition, thefrequency synthesizer signal (f_(synth)) may be divided by 2 byfrequency divider 360 and input via line 353 to mixer 262 and mixer 462.This signal (f_(synth)/2) received via line 353 may be used byquadrature mixers 262 and 462 to down convert lower band signals (e.g.,EGSM900 and GSM850 signals) to IF (e.g., 200 KHz), for example.

FIG. 4 is a block diagram of a receiver according to an exampleembodiment. Receiver 404 shown in FIG. 4 may replace (or be substitutedfor) receiver 204 in wireless transceiver 102 (FIG. 2), for example.Variable gain LNAs 460 may receive signals from different bands, e.g.,LNA 460A may receive signals from PCS1900, LNA 460B may receive signalsfrom DCS1800, LNA 460C may receive signals from EGSM900, and LNA 460Dmay receive signals from GSM850. As noted above, the PCS1900 and DCS1800may be considered an upper band of RF signals, while EGSM900 and GSM850may be considered a lower band of RF signals. In an example embodiment,in operation (non-calibration) mode, only one of LNAs 460 may be activeat a time, based on a channel that has been selected or assigned towireless transceiver 102 for receiving signals.

Quadrature mixers 462 are coupled to LNAs 460 to down convert thereceived signal to an IF signal (e.g., at 200 KHz). An output of upperband LNAs 460A and 460B are input to in-phase mixer 462A andquadrature-phase mixer 462B to generate in-phase (I) and quadraturephase (Q) signals, respectively, at IF based on a mixing signal(f_(synth)) input to mixers 462 via line 350. Similarly, an output fromlower band LNAs 460C and 460D are input to in-phase (I) mixer 462C andquadrature-phase (Q) mixer 462D. In-phase mixer 462C andquadrature-phase mixer 462D generate in-phase (I) and quadrature phase(Q) signals, respectively, at IF based on the received lower band RFsignal (e.g., GSM850 signal or EGSM900 signal) and based on a mixingsignal (f_(synth)/2) input to mixers 462 via line 353. Quadrature-phasemixers 462B and 462D may also, for example, introduce a 90 degree phaseoffset (or a predetermined phase offset), for example.

A receiver IF block 465 is coupled to an output of mixers 462 to performIF processing. The in-phase (I) and quadrature-phase (Q) signals outputby mixers 462 are input to an in-phase portion 458A and aquadrature-phase portion 458B, respectively, of receiver IF block 465.In-phase portion 458A may include, for example, a tunable (oradjustable) band-pass filter (BPF) 450A to filter the received analog Isignal, a variable gain amplifier 452A to amplify the output from BPF450A, and an analog-to-digital converter (ADC) 454A to convert thefiltered and amplified analog in-phase signal to a digital form.Similarly, Q-phase portion 458B of receiver IF block 465 may include aBPF 450B, a variable gain amplifier 452B and an ADC 454B to similarlyprocess the quadrature-phase (Q) signal from mixers 462. In an exampleembodiment, BPFs 450 may also include a variable gain. In an exampleembodiment, ADCs 454A and 454B may be relatively high dynamic range,14-bit delta-sigma (ΔΣ) ADCs, with, for example, approximately 88 dB ormore of dynamic range. The use of a relatively high dynamic range ADCmay, for example, allow a wide range of signal amplitudes to be received(including both a desired signal and an image signal(s)) and convertedto digital form without saturating the ADC. This is merely one exampleembodiment for ADCs 454, and others may be used. The 200 KHz digital Iand Q signals output from receiver IF 465 are input to a receiverdigital processor, such as a digital signal processor (DSP) 466, forfurther processing as digital signals (digital processing). For example,receiver DSP 466 may perform additional filtering, gain (amplitude) andphase control, and down conversion for each of the received digital Iand Q IF signals. As described in more detail below, the receiver DSP466 may also perform a digital I/Q calibration to improve the rejection(or cancellation) of image signals at the receiver 404.

The use of an IF frequency at or around 200 KHz, as an example, allowsBPFs 450A and 450B to effectively or substantially filter the receivedsignal and thereby remove a DC offset in the received analog I and Qsignals, for example. A relatively high IF frequency (such as 200 KHz)also may have an advantage of being less sensitive to flicker nose,frequency noise, and may have a higher IIIP2 (second order inputintercept point). However, such a high IF may present some challenges inthe rejection or cancellation of image signals. Due to the operation ofmixers 462, an image signal at an image frequency that may be, forexample 2*IF away from the desired (channel) frequency may typically bereceived and also down converted by mixers 462. For example, an imagesignal that is 400 KHz away from the desired signal frequency may bedown converted by mixers 462 to −200 KHz. Thus, the desired signal at anIF of 200 KHz and the image signal at a down converted frequency of −200KHz may both be input to receiver IF 465. In an example embodiment, BPFs450A and 450B may typically pass both the desired signal (at 200 KHz)and the image signal (at −200 KHz). After being converted to a digitalform, the receiver DSP may down convert the received signals (desiredsignal at 200 KHz and image signal at −200 KHz) to baseband frequency,and in the process may substantially cancel or reject the image signal.Imperfections in equipment, etc. and mismatches in the I and Q signalsmay impact the receiver's ability to reject or cancel the image signal.

However, in some cases, according to an example embodiment, the receiver404 may need to reject an image that may be, for example, up to 50 dBgreater than the desired signal. In order to provide such a significantimage rejection, it may be beneficial for the digital I and Q signals(that are being converted to baseband) to be substantially the sameamplitude and substantially 90 degrees out of phase (predetermine phaseoffset), to facilitate an effective rejection or cancellation of theimage signal, for example. Any significant mismatches in amplitude ormismatch from the predetermined phase offset (e.g., less than or greaterthan 90 degree offset) for the digital I and Q signals may, at least insome cases, decrease the ability of receiver 404 to reject or cancel animage signal.

Therefore, according to an example embodiment, an I/Q calibration may beperformed by receiver 404 based on signals provided or output bytransmitter 202 in a calibration mode. According to an exampleembodiment, in a calibration mode, after receiving a channel assignmentfrom an access point or base station, the transmitter 202 may determinea frequency of an image signal for the channel. The transmitter may thenoutput a signal that is up converted by mixer 256 to an image frequency,e.g., a frequency that may be 400 KHz (or 2*IF) from the desired channelfrequency. This signal output from transmitter 202 via loop back (e.g.,output from amplifier 222 or 226, and fed back through mixer 256) toreceiver 404 may be considered to be a simulated image signal at animage frequency for the channel. This simulated image signal may then bedown converted by quadrature mixers 462 to an IF, e.g., −200 KHz, andproduce analog I and Q signals at this frequency. (Note that the IFfrequency may vary, based on the frequency of the received signal, andmay be 200 KHz typically for a selected or desired channel, and may befor example, −200 KHz when processing and down converting an imagesignal or simulated image signal).

BPFs 450 may pass the I and Q analog signals, which are converted todigital form. Receiver DSP 466 may determine digitally a receiverin-phase/quadrature-phase (I/Q) signal calibration adjustment based onthe image signal to improve a match in amplitudes and a predeterminedphase shift (e.g., 90 degrees) between I and Q signals of the receiverduring a calibration mode of operation.

Such an I/Q calibration may be performed, for example, by receiver DSP466 determining a mismatch in amplitudes and mismatch in predeterminedoffset in phase between the digital I and Q signals from the imagesignal. The mismatch (or error) in predetermined phase offset mightoccur where the phases of the I and Q signals are less than or greaterthan the predetermined phase offset (e.g., less than or greater than 90degrees). The receiver DSP 466 may digitally determine a receiver I/Qcalibration adjustment to compensate for the mismatch in amplitudes andpredetermined phase for the received I/Q components from the simulatedimage signal.

The I/Q calibration adjustment may be, for example, an adjustment inamplitude and/or phase for one or both of the I/Q signals. In anoperation mode, with the transceiver 102 operating (or receivingsignals) on the assigned channel for which I/Q calibration has beenperformed using a simulated image signal for the channel, receiver DSP466 may then digitally apply the I/Q calibration adjustment to thereceived digital I and Q signals. The application or use of the I/Qcalibration adjustment at the receiver 404 may improve the rejection orcancellation of an image signal during an operation mode, e.g., byplacing or adjusting the amplitudes of the digital I/Q signals tosubstantially the same amplitude and adjusting the phase offset tosubstantially a predetermined offset.

In addition, the I/Q calibration may be repeated for each (or even all)of the channels, e.g., during a calibration mode for the transceiver102, since the I/Q calibration adjustment may be different for eachchannel or frequency, and may also vary based on temperature and othervariable conditions. In one example embodiment, the I/Q calibration maybe repeated before the wireless transceiver receives each packet. Byperforming I/Q calibration for each packet, for example, this may allowsuch calibration to adapt (or be insensitive) to a transceiver'schanging channels or frequencies. In addition, within each channel, theI/Q calibration may be performed over a variety of tones or frequenciesacross the 200 KHz BPF pass band, to provide better I/Q calibrationwithin the channel, e.g., may perform I/Q calibration for each of, e.g.,10 or 100 or more tones or frequencies within a 200 KHz pass band, forexample.

Referring to FIG. 4 again, LNAs 460 may provide an analog gain for thereceiver input signal. In addition, amplifiers 452 may provideadditional analog gain. Each amplifier 452 may be provided as part of aBPF 450 or associated with a BPF 450, in an example embodiment. Thus,amplifiers 452 may also be referred to as BPF amplifiers, for example.The receiver analog gain may be considered to be, for example, thevariable LNA gain (provided by LNA 460) plus the variable BPF gain(provided by BPF amplifier 452). Receiver DSP 466 also provides avariable digital gain on received digital signals.

According to an example embodiment, the analog and digital gains ofreceiver 404 may be varied, for example, based on the level (oramplitude) of the receiver input signal. FIG. 5 is a chart illustratingan example gain control for the receiver of FIG. 4 according to anexample embodiment. The gain control may include, for example, varyingthe gain provided by one or both analog amplifiers (or analog gaincircuits), including LNAs 460 and BPF amplifiers 450. The gain controlmay also include varying the gain for the post-ADC digital gain providedby receiver DSP 466.

In FIG. 5, input range 502 identifies the level (or amplitude) of thereceiver input signal (e.g., input to LNAs 460). LNA gain 504 identifiesthe gain provided by LNAs 460, BPF gain 506 identifies the gain providedby BPF amplifier 452 (or in general the gain provided by receiver IFsection 465) and digital gain 510 identifies the gain provided byreceiver DSP 466. The analog gain 508 may be calculated as: Analog gain(508)=LNA gain+BPF gain−6 dB (receiver front end loss). Thus, the analoggain 508 may be the sum of the two analog gains (LNA gain 504 and BPFgain 506), minus a front end receiver loss of 6 dB, for example. Thetotal gain 512 may be calculated as: total gain (512)=analog gain(508)+digital gain (510). Thus, the total gain 512 for receiver 404 maybe the sum of the analog gain 508 and the digital gain 510. The ADCinput signal level (ADC In) 514 identifies the level of the signal inputto the ADC 454. In some cases, it is desirable to maintain the level ofthe ADC input level 514 at a high level so as to use significant amountof the dynamic range of the ADCs 454, but not too high so as to saturatethe ADC 454 in the presence of blockers (or blocker signals). ADC inputlevel 514 may be calculated as: ADC input level (514)=receiver input(502)+analog gain (508). The gains (LNA gain 504, BPG gain 506, analoggain 508, digital gain 510 and total gain 512) shown in FIG. 5 may beprovided in dB, while the signal levels (receiver input signal 502 andADC input signal 514) may be provided in dBm, for example.

Referring to FIG. 5, for very low receiver input signals 502, e.g., −109dBm to −104 dBm, the LNA gain 504 may be set to a highest or arelatively high value of 30 dBm, the BPF gain 506 may be set to 35 dBand decreasing as input signal increases, and the digital gain 510 maybe set to a substantially constant value of 30 dB, for example. Thus,the total gain 512 is initially set to a fairly high value, such as 89dB so receiver 404 may be sensitive to very low amplitude signals. Thetotal gain 512 may typically decrease as the receiver input signal 502increases. According to an example embodiment, the analog and digitalgains may be adjusted to provide a substantially constant receiveroutput signal level (e.g., output by receiver DSP 466). Thissubstantially constant receiver output signal level, which may be −20dBm, for example, may provide baseband processor 112 a substantiallyconstant and predictable input signal for processing, in an exampleembodiment.

As the receiver input signal level 502 increases from −109 dBm to −99dBm, a blocker test may be applied to the receiver at around −99 dBm, inan example embodiment. A blocker test may include for example, applyinga blocker signal at a specific frequency and amplitude to determine ifthe receiver can sufficiently obtain the desired signal in the presenceof such a blocker. Many of the various wireless standards, such as GSM,EGSM, etc., have specific tests which wireless devices may be requiredto pass, such as a blocker test. In an example embodiment, the analoggain 508 may be decreased as the receiver input signal level increases,while maintaining the digital gain 510 substantially constant at −50 dB,for example. This decrease in analog gain allows the LNAs 460 to handlea larger blocker signal without saturating the LNAs, and may betterallow the receiver to pass the blocker test. In an example embodiment,the LNA gain 504 may be decreased from 30 dB to 25 dB prior to the −99dBm receiver input signal level 502 for the blocker test, to betterallow a larger blocker signal to be received along with the desiredsignal, without saturating the LNAs 460 and BPF amplifiers 452, forexample. In an example embodiment, when the LNA gain 504 decreases to 25dB for better blocking tolerance, the signal is stronger and the noisefigure degradation is acceptable.

As the receiver input signal level (502) increases to a level greaterthan the blocker test signal level (e.g., −99 dBm), the analog gain 508may continue to decrease while the digital gain 510 may continue to bemaintained substantially constant, for example. Also, the ADC input 514may also continue to be maintained at a substantially constant level of−50 dBm, for example. Continuing to decrease the analog gain 508 andmaintaining the ADC input level 514 at −50 dBm may better allow receiver404 to receive the desired signal and an image signal without saturatingthe ADCs 454. An image test may be applied at a receiver input signal502 of around −80 dBm, in an example embodiment. The image signal may beapplied up to 50 dB greater than the desired signal. Thus, in an exampleembodiment, the digital gain 508 and the ADC input level may bemaintained at a constant level, while decreasing the analog gain 508, atleast up to the image test (e.g., −80 dBm for input signal 502), toallow the ADC 454 to receive and pass both the desired signal and imagesignal without the ADC 454 being saturated, for example. In an exampleembodiment, just before the image test, the LNA gain 504 may bedecreased from 25 dB to 20 dB to better accommodate a larger imagesignal without saturating ADC 454, for example. According to an exampleembodiment, when the image test is being performed, it may beadvantageous to maintain the ADC input signal level 514 at a relativelylow signal level, such as −50 dBm (for example), in order to handle theimage blocker which may be as much as 50 dB higher than the desiredsignal.

For receiver input signals 502 that are greater than −80 dBm (e.g.,levels beyond the image test), statistically, image signals and blockersignals are not expected to be a problem. In addition, it may bedesirable to increase the ADC input level 514 to make more complete useof the full dynamic range of the ADCs 454. Therefore, according to anexample embodiment, for receiver input signals greater than −80 dBm upto approximately −44 dbM (for example), the analog gain 508 may bemaintained at a substantially constant level, while the digital gain 510decreases from 30 dB to 0 dB. Keeping the analog gain 508 substantiallyconstant for receiver input signal levels 502 approximately between, forexample, −71 dBm and −44 dBm may allow the ADC input level 514 toincrease from −50 dBm to approximately −20 dBm, for example. In thismanner, increasing the ADC input level 514 (e.g., by holding analog gainsubstantially constant as input signal levels increase and decreasingdigital gain) may allow a better use of the full dynamic range of theADC 454, for example.

In an example embodiment, a down-fading test may be applied at areceiver input signal level 502 of around −50 dBm, for example. Theincrease in ADC input level 514 from −50 dBm to approximately −27 or −25dBm may provide additional dynamic range for the ADC 454 which may beuseful in passing the down-fading test. After the down-fading test, thedigital gain 510 and the analog gain 508 (including both LNA gain andBPF gain) are continually decreased until they reach zero, to allow forlarger signals to be accommodated without saturating the variouscomponents of the receiver.

FIG. 6 is a flow chart illustrating operation of a wireless receiveraccording to an example embodiment. For example, the flow chart of FIG.6 may describe a method of varying an analog gain and a digital gain ina wireless receiver. At 610, an analog gain is decreased whilemaintaining a digital gain substantially constant for a receiver inputsignal to the receiver that increases from a first input signal level upto at least a first test signal level (e.g., up to a blocker test signallevel or up to an image test signal level). Decreasing the analog gains,for example, may allow the receiver to better pass the blocker testand/or image test, and handle larger blocker signals without saturatingthe LNAs and/or ADCs.

At 620, the analog gain may be maintained substantially constant whiledecreasing the digital gain for a receiver input signal level thatincreases from the first test signal level up to at least a second inputsignal level. According to an example embodiment, maintaining the analoggain substantially constant while decreasing the analog gain as receiverinput signal increases may allow the ADC input level to be increased toallow better use of the full dynamic range of the ADCs, especially forreceiver input signals beyond (or greater than) the blocker test and/orimage test.

At 630, a substantially constant signal level is maintained for adigital output of the receiver. This may be done, for example, bydecreasing the overall gain (e.g., by varying the analog gain and/ordigital gain) as the received input signal increases, such that thelevel of the output signal maintains a constant level. The may provide asubstantially constant and predictable receiver output signal level thatmay be input to baseband processor 112.

FIG. 7 is a flow chart illustrating operation of a wireless receiveraccording to another example embodiment. According to an exampleembodiment, FIG. 7 may describe a method of varying gain in a wirelessreceiver. The wireless receiver may include, for example, ananalog-to-digital converter (ADC), an analog gain circuit coupled to aninput of the ADC, and a digital gain circuit coupled to an output of theADC.

At 710, a gain of the analog gain circuit is varied to maintain asubstantially constant signal level at an input to the ADC whilemaintaining the gain of the digital gain circuit at a substantiallyconstant level as the input signal to the receiver varies between afirst input signal level up to a first test signal level. For example,the analog gain circuit may include a first analog amplifier coupled toreceive the receiver input signal and a second analog amplifier. Thevarying (710) may include the first analog amplifier providing a firstdecrease in gain at a receiver input signal level less than or equal toa blocker test signal level, and the first analog amplifier providing asecond decrease in gain at a receiver input signal level less than orequal to an image test signal level.

At 720, the gain of the analog gain circuit is maintained substantiallyconstant while decreasing the gain of the digital gain circuit for areceiver input signal level that increases from the first test signallevel up to at least a second input signal level.

At 730, a gain of the analog gain circuit is further varied (e.g.,decreased) as the receiver input signal increases from the second inputsignal level up to a third input signal level, while maintaining areceiver output signal at a constant level.

As noted above, the output signal from transmitter 202 may be loopedback or fed back into receiver 204/404, to perform I/Q calibration.According to an example embodiment, the output level or amplitude of thetransmit test signal looped back into the receiver for I/Q calibrationmay be adjusted based on the receiver gain. For example, as the receivergain (e.g., total gain 512) decreases, the level of the transmit testsignal may be increased. Or, in another example embodiment, the transmitsignal level used for loopback I/Q calibration may be varied inverselyas the receiver gain changes.

While certain features of the described implementations have beenillustrated as described herein, many modifications, substitutions,changes and equivalents will now occur to those skilled in the art. Itis, therefore, to be understood that the appended claims are intended tocover all such modifications and changes as fall within the true spiritof the various embodiments.

1. A method of varying an analog gain and a digital gain in a wirelessreceiver comprising: decreasing an analog gain while maintaining adigital gain substantially constant for a signal level of an inputsignal to the receiver that increases from a first input signal level upto at least a first test signal level; and maintaining the analog gainsubstantially constant while decreasing the digital gain for an inputsignal level of the receiver that increases from the first test signallevel up to at least a second input signal level.
 2. The method of claim1 wherein the decreasing comprises decreasing an analog gain whilemaintaining a digital gain substantially constant for a signal level ofan input signal to the receiver that increases from a first input signallevel up to at least a blocker test signal level.
 3. The method of claim1 wherein the decreasing comprises decreasing an analog gain whilemaintaining a digital gain substantially constant for a signal level ofan input signal to the receiver that increases from a first input signallevel up to at least an image test signal level.
 4. The method of claim1 and further comprising maintaining a substantially constant signallevel for a digital output of the receiver.
 5. A method of varying gainin a wireless receiver, the wireless receiver including ananalog-to-digital converter (ADC), an analog gain circuit coupled to aninput of the ADC, and a digital gain circuit coupled to an output of theADC, the method comprising: varying a gain of the analog gain circuit tomaintain a substantially constant signal level at an input to the ADCwhile maintaining the gain of the digital gain circuit at asubstantially constant level as the input signal to the receiver variesbetween a first input signal level up to a first test signal level; andmaintaining the gain of the analog gain circuit substantially constantwhile decreasing the gain of the digital gain circuit for a receiverinput signal level that increases from the first test signal level up toat least a second input signal level.
 6. The method of claim 5 andfurther comprising: further varying a gain of the analog gain circuit asthe receiver input signal increases from the second input signal levelup to a third input signal level, while maintaining a receiver outputsignal at a constant level.
 7. The method of claim 5 wherein the varyingcomprises varying a gain of the analog gain circuit to maintain asubstantially constant signal level at an input to the ADC whilemaintaining the gain of the digital gain circuit at a substantiallyconstant level as the input signal to the receiver varies between afirst input signal level up to a blocker test signal level.
 8. Themethod of claim 5 wherein the varying comprises varying a gain of theanalog gain circuit to maintain a substantially constant signal level atan input to the ADC while maintaining the gain of the digital gaincircuit at a substantially constant level as the input signal to thereceiver varies between a first input signal level up to an image testsignal level.
 9. A method of varying gain in a wireless receiver, thewireless receiver including an analog-to-digital converter (ADC), ananalog gain circuit coupled to an input of the ADC, and a digital gaincircuit coupled to an output of the ADC, the method comprising: varyinga gain of the analog gain circuit to maintain a substantially constantsignal level at an input to the ADC while maintaining the gain of thedigital gain circuit at a substantially constant level as the inputsignal to the receiver varies between a first input signal level up to afirst test signal level; and wherein the amplitude gain circuitcomprises a first analog amplifier coupled to receive the input signaland a second analog amplifier; and the varying comprising: the firstanalog amplifier providing a first decrease in gain at a receiver inputsignal level less than or equal to the first test signal level, and thefirst analog amplifier providing a second decrease in gain at a receiverinput signal level less than or equal to a second test signal level. 10.A method of varying gain in a wireless receiver, the wireless receiverincluding an analog-to-digital converter (ADC), an analog gain circuitcoupled to an input of the ADC, and a digital gain circuit coupled to anoutput of the ADC, the method comprising: varying a gain of the analoggain circuit to maintain a substantially constant signal level at aninput to the ADC while maintaining the gain of the digital gain circuitat a substantially constant level as the input signal to the receivervaries between a first input signal level up to a first test signallevel; and wherein the amplitude gain circuit comprises a first analogamplifier coupled to receive the input signal and a second analogamplifier; and the varying comprising: the first analog amplifierproviding a first decrease in gain at a receiver input signal level lessthan or equal to a blocker test signal level, and the first analogamplifier providing a second decrease in gain at a receiver input signallevel less than or equal to an image test signal level.
 11. The methodof claim 9 wherein the varying comprises varying a gain of the analoggain circuit to maintain a substantially constant signal level at aninput to the ADC while maintaining the gain of the digital gain circuitat a substantially constant level as the input signal to the receivervaries between a first input signal level up to a blocker test signallevel.
 12. The method of claim 9 wherein the varying comprises varying again of the analog gain circuit to maintain a substantially constantsignal level at an input to the ADC while maintaining the gain of thedigital gain circuit at a substantially constant level as the inputsignal to the receiver varies between a first input signal level up toan image test signal level.
 13. The method of claim 10 wherein thevarying comprises varying a gain of the analog gain circuit to maintaina substantially constant signal level at an input to the ADC whilemaintaining the gain of the digital gain circuit at a substantiallyconstant level as the input signal to the receiver varies between afirst input signal level up to a blocker test signal level.
 14. Themethod of claim 10 wherein the varying comprises varying a gain of theanalog gain circuit to maintain a substantially constant signal level atan input to the ADC while maintaining the gain of the digital gaincircuit at a substantially constant level as the input signal to thereceiver varies between a first input signal level up to the image testsignal level.